Contributions to Standards Committees
VHDL (IEEE 1076)
I joined the VHDL International (VI) ASIC library standardization project, the VHDL Initiative towards ASIC Libraries (VITAL), as it completed its first implementation. While much of the code was written for the 2.2b release, I took on the task to promote it to a worldwide community with a day-long technical seminar to train ASIC library developers. This presentation was also shared with other VI members to help them promulgate this emerging standard. VI transferred ongoing maintenance and standardization to the IEEE and I joined the IEEE 1076.4 Timing Working Group TAG and eventually became the TAG chair, then working group chair.
In the mid 1990’s I pioneered the use of the web to explore how the ASIC library community could learn VITAL by building models, submitting them via email and getting results back to determine if the models they were creating worked correctly. This was all done prior to the worldwide web and at a time when VI’s only collaboration system was vhdl.org (now known as eda.org) that was accessed via a bank of modem connections to a bulletin board system. I also drove collaboration with Si2 to expand their IEEE 1364 Verilog ASIC library testing to conformance with the IEEE 1076.4 VITAL standard.
DPCS (IEEE 1481)
Having successfully completed an IEEE standardization round for 1076.4, I was asked to help VI, OVI and Si2 bring together components of a standard for the Delay and Power Calculation Standard (DPCS) that included Si2’s DCL and OVI’s PDEF & SPEF. I successfully negotiated equal support by all three organizations, sidestepping the normal political issues that can arise. I worked to get IP contributors to alter their contracts to have them adhere to the IEEE policies with respect to technology donations.
During this time, I assumed the VI and OVI director positions for Mentor Graphics. And, in a leadership gap for OVI, I was willing to fill the chair role understanding that with the natural tendency for the Big-3 EDA companies to argue, being at the helm was going to require transparency and strict adherence to rules and policy in order to show no favoritism or undue influence on the work program of OVI. At that time, I supported the move within VI and OVI to explore support of system-level languages. Progress was initially slow. As I challenged the OVI technical chair to focus on possible solutions by working with members and other groups around the world, I also reached out to the VI chair to explore combining forces to address the system challenges. The two organizations subsequently merged.
Verilog and SystemVerilog (IEEE 1364 & IEEE 1800)
Dennis and Gabe merged OVI and VI to create Accellera with support and assistance of many. Technical leadership and active member participation resulted in several areas of work that have become accepted industry standards such as PSL, SystemVerilog (Assertions, Testbench, etc.), and many others.
Dennis has been the vice chair and secretary of the IEEE 1800 SystemVerilog Working Group since its beginning in 2003, working with Chair Karen Pieper for nearly 10 years. Besides facilitating the operational aspects of the IEEE 1800 WG, he provides guidance on the overall standardization process. He has been one of the strongest proponents of SystemVerilog, visiting worldwide locations to promote it at conferences, seminars and user group events.
UPF, UVM, and UCIS (IEEE 1801 & Accellera Accessory Standards)
Dennis has been the face of several Accellera standards in their infancy. It is not far from reality that he has been the initiator of UPF (low power), UVM (verification) and UCIS (coverage) standards in Accellera. All these standards are currently very active in the industry and their adoption rate continues to grow, thanks to many promotional activities initiated and supported by Dennis through Accellera, IEEE, and his employer, Mentor Graphics.